1. Field of the Invention
This invention relates to an electrically rewritable and non-volatile semiconductor memory device (EEPROM), specifically relates to an improvement of the bad address register scheme.
2. Description of the Related Art
A NAND-type flash memory is well-known as a typical one of EEPROMs. In the currently manufactured NAND-type flash memories, even if bad blocks are detected in the die-sort test, it is allowed of bad blocks, the number of which is less than a certain value. The reason is as follows: allowing of the bad blocks, the number of which is less than a certain value, it becomes possible to increase the throughput of the device.
However, it is required of the bad blocks to be controlled in a scheme different from the normal blocks. For example, the bad block addresses must be registered in a ROM fuse area defined in the memory cell array. The bad block addresses registered in the ROM fuse area will be read out in a power-on reset operation executed every power-on time, and the corresponding row decoders are selected, whereby bad block flags are set in the bad block flag latches in these row decoders.
Once a bad block flag is set in a row decoder, the corresponding block is recognized as a bad block by the memory controller, and it becomes possible to control the memory so as to estimate the influence of the bad block (for example, refer to JP-A-2001-273798).
The bad block address register scheme will be explained in detail in such a case that a memory chip is formed of one plane with 1024 blocks, and the capacity of one page is 1 k Byte. It is necessary for this chip with 1024 blocks to express the block addresses by 10 bits. In a usual data processing, 8 bits (=1 Byte) constitute a data unit. Therefore, to register one block address, it is in need of preparing an area of 2 Byte.
On the other hand, since it is required of the ROM fuse area to have a high reliability, complementary data will be used. Comparing true data with complementary data at a read time, it becomes possible to secure a high reliability. In this case, in order to register one block address, it will be necessary to use an area of 4 Byte.
Further, considering such a situation that a data error occurs due to the data comparison, it is desired to use multiple data sets each constituted by true data and complementary data. Assuming that two data sets are prepared, it becomes necessary to use an area of 8 Byte for registering one block address. In this case, it should be noted that only 128 blocks can be registered in a NAND-type flash memory, one page capacity of which is 1 k Byte.
If there are 129 or more bad blocks detected in a chip with 1024 blocks in the above-described example, the chip is dealt with as a bad one, and will not be shipped.